There are oscillators and filters that include a switching capacitor generation circuit to select a capacitor that is coupled to the oscillator or filter with a switching element and thereby adjust the oscillation frequency or cutoff frequency. The switching capacitor generation circuit selects whether or not to couple the capacitor via a switching element, which is formed by a MOS transistor. The operation properties of such a switching element must be improved.
FIG. 13 shows a prior art voltage-controlled oscillator (hereinafter referred to as VCO) coupled to capacitor arrays 1a and 1b, which include switching elements. In the VCO, an oscillator 2 includes two inverter circuits, the input/output terminals of which are coupled to each other. An inductance 3 is coupled between output terminals OUT1 and OUT2 of the inverter circuits, and variable capacitors 4a and 4b, which are coupled in series, are coupled between the two terminals of the inductance 3. The inductance 3 and the variable capacitors 4a and 4b form an LC oscillation circuit.
When a control voltage VT is supplied to the node between the variable capacitors 4a and 4b, the oscillator 2 outputs an output signal that oscillates at a frequency that is based on the control voltage VT from the output terminals OUT1 and OUT2.
The capacitor arrays 1a and 1b, which adjust the oscillation frequency of the oscillator 2, are coupled to the output terminals OUT1 and OUT2, respectively. Since the capacitor arrays 1a and 1b have the same configuration, only the capacitor array 1a will be described here.
The capacitor array 1a includes a plurality of switching capacitor generation circuits (three in FIG. 13), which are coupled in parallel, between the output terminal OUT1 and a power supply Vss, which is a low potential power supply. The switching capacitor generation circuits each include a capacitor (C1, C2, C4 in the drawing and a switch element SW, which is formed by an N-channel MOS transistor and coupled in series to the capacitor. The capacitance values of the capacitors C1, C2, C4, . . . is weighed so as to be 1:2:4 . . . .
Control signals V1, V2, and V4 respectively provided to the switching elements SW open and close the switch elements SW. The capacitor coupled to the switching element SW switched to a conductive state acts on the output terminal OUT1. In the capacitor arrays 1a and 1b, the switch elements SW are respectively controlled by the control signals V1, V2, and V4 so that the capacitance values coupled to the output terminals OUT1 and OUT2 become the same.
In the VCO, the frequency of the output signal output from the output terminals OUT1 and OUT2 is adjusted by adjusting the capacitance value of the capacitor arrays 1a and 1b, which are coupled to the output terminals OUT1 and OUT2, with the control signals V1, V2, and V4.
Such a VCO is used, for example, in a PLL circuit, for example. The adjustment of the capacitor arrays 1a and 1b roughly adjusts the frequency of the output signal. In this state, the control voltage VT generated by a PLL loop further adjusts the frequency of the output signal.
The VCO oscillates at a high frequency in the switching capacitor generation circuit used in the capacitor array 1a, 1b. Thus, the conditions described below are necessary.
First, when the switch element SW is in a conductive state. It is desirable that the on-resistance of the switch element SW be decreased. If the on-resistance is decreased, the capacitors coupled to the output terminals OUT1 and OUT2 of the oscillator 2 are efficiently operated thereby improving the quality factor. Thus, the N-channel MOS transistor forming the switch element SW must have a large gate width and a short gate length.
Further, when the switch element SW is in a non-conductive state, it is desirable that a parasitic capacitor Cp of the switch element SW shown in FIG. 14 be reduced. When the parasitic capacitor Cp of the switch element SW becomes large, the change in the capacitance value that acts on the output terminal becomes small when the switch element SW is in a conductive state and a non-conductive state. When reducing the size of the parasitic capacitor Cp, the N-channel MOS transistor forming the switch element SW must have a small gate width and a long gate length to reduce the size of the parasitic capacitor generated between the drain of the N-channel MOS transistor and the P-well.
Accordingly, the gate width must be increased to improve the quality factor when the switch element SW is in a conductive state, and the gate width must be decreased to reduce the size of the parasitic capacitor Cp when the switch element SW is in a non-conductive state. It is difficult to satisfy both of these conditions at the same time.
Patent document 1 discloses a sense amplifier circuit similar to the circuit configuration of the oscillator 2. However, there is not disclosure related to the quality factor and parasitic capacitance of the capacitor array. Patent document 1: Japanese Laid-Open Patent Publication No. 11-176163